Adlink DAQe-2006 Manual de usuario Pagina 80
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68 Operation Theory
4.6 User-controllable Timing Signals
In order to meet the requirements for user-specific timing and
requirements for synchronizing multiple cards, the DAQ-/DAQe-/
PXI-2016/2010/2006/2005 card provides flexible user-controllable
timing signals to connect to external circuitry or additional cards.
The whole DAQ timing of the DAQ-/DAQe-/PXI-2016/2010/2006/
2005 card is composed of a bunch of counters and trigger signals
in the FPGA. These timing signals are related to the A/D, D/A con-
versions, and Timer/Counter applications. These timing signals
can be input to or output from the I/O connectors, SSI connector,
and the PXI bus. Therefore, the internal timing signals can be
used to control external devices or circuitry. Note that in other
models of DAQ-/DAQe-/PXI-2016/2010/2006/2005 card, the user-
controllable timing signals may vary. However, the SSI/PXI timing
signals remain the same for every DAQ-/DAQe-/PXI-2016/2010/
2006/2005 card.
We implemented signal multiplexers in the FPGA to individually
choose the desired timing signals for the DAQ operations, as
shown in the Figure 4-38
Figure 4-38: DAQ signals routing
You can utilize the flexible timing signals through our software
drivers, then simply and correctly connect the signals with the
DAQ-/DAQe-/PXI-2016/2010/2006/2005 cards. Here is the sum-
mary of the DAQ timing signals and the corresponding functional-
ities for DAQ-/DAQe-/PXI-2016/2010/2006/2005 card.
- DAQ-/DAQe-/PXI 1
- 2016/2010/2006/2005 1
- Getting service 3
- Using this manual 5
- 1.3 Conventions 6
- Table of Contents 7
- List of Tables 9
- List of Figures 10
- List of Figures v 11
- 1 Introduction 13
- 1.1 Features 14
- 1.2 Applications 15
- 1.3 Specifications 16
- System Noise: (Typical) 17
- Gain error: 20
- 2005/2006/2016 20
- Ω typical 21
- 10 Introduction 22
- Ω for DAQ-/DAQe-/PXI-2010 23
- °C to 55°C 24
- °C to 80°C 24
- 1.4 Software Support 25
- DAQ-LVIEW PnP: LabVIEW Driver 26
- D2K-OCX: ActiveX Controls 26
- 2 Installation 27
- 16 Installation 28
- 2.3 Card Layout 29
- DAQ-2016/2010/2006/2005 30
- PXI-2016/2010/2006/2005 30
- 2.4 PCI Configuration 31
- 20 Installation 32
- 3 Signal Connections 33
- VHDCI-type (68-pin) Connector 34
- *PIO means programmable I/O 36
- SSI Connector (J3) 37
- Types of signal sources 38
- Single-Ended Measurements 38
- Differential Measurements 39
- 28 Signal Connections 40
- 4 Operation Theory 41
- 34 Operation Theory 46
- Ch1 with unipolar ±10V 46
- Ch2 with bipolar ±2.5V 46
- Ch4 with bipolar ±1.25V 46
- 36 Operation Theory 48
- Figure 4-3: Scan Timing 48
- Trigger Modes 49
- PSC_counter = 0 50
- Operation Theory 39 51
- 40 Operation Theory 52
- Operation Theory 41 53
- Figure 4-9: Middle-Trigger 53
- 42 Operation Theory 54
- Figure 4-10: Post trigger 54
- Operation Theory 43 55
- Figure 4-11: Delay trigger 55
- 44 Operation Theory 56
- Operation Theory 45 57
- 46 Operation Theory 58
- 4.2 D/A Conversion 59
- Software Update 60
- Timed Waveform Generation 61
- 50 Operation Theory 62
- 52 Operation Theory 64
- Operation Theory 53 65
- DLY2_Counter = 0 65
- 54 Operation Theory 66
- Operation Theory 55 67
- Figure 4-20: Stop Mode I 67
- 56 Operation Theory 68
- Figure 4-21: Stop Mode II 68
- Figure 4-22: Stop Mode III 68
- 4.3 Digital I/O 69
- 58 Operation Theory 70
- Figure 4-23: Mode 1 Operation 70
- Operation Theory 59 71
- Figure 4-24: Mode 2 Operation 71
- 60 Operation Theory 72
- Figure 4-25: Mode 3 Operation 72
- Figure 4-26: Mode 4 Operation 72
- Operation Theory 61 73
- Figure 4-27: Mode 5 Operation 73
- Figure 4-28: Mode 6 Operation 73
- 62 Operation Theory 74
- Figure 4-29: Mode 7 Operation 74
- Figure 4-30: Mode 8 Operation 74
- 4.5 Trigger Sources 75
- Operation Theory 65 77
- 66 Operation Theory 78
- Operation Theory 67 79
- 68 Operation Theory 80
- DAQ timing signals 81
- 72 Operation Theory 84
- 74 Operation Theory 86
- AI_Trig_Out and AO_Trig_Out 87
- 76 Operation Theory 88
- 5 Calibration 89
- 5.2 Auto-calibration 90
- Warranty Policy 91
- 80 Warranty Policy 92
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