Adlink DAQe-2006 Manual de usuario Pagina 34
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Valorado. / 5. Basado en revisión del cliente
22 Signal Connections
VHDCI-type (68-pin) Connector
*SDI for DAQ/DAQe/PXI-2010 only. NC for DAQ/DAQe/PXI-2005/
CH0+ 1 35 CH0-
CH1+ 2 36 CH1-
CH2+ 3 37 CH2-
CH3+ 4 38 CH3-
EXTATRIG 5 39 AIGND
DA1OUT 6 40 AOGND
DA0OUT 7 41 AOGND
AOEXTREF 8 42 AOGND
SDI3_1 / NC* 9 43 SDI3_0 / NC*
SDI2_1 / NC* 10 44 SDI2_0 / NC*
SDI1_1 / NC* 11 45 SDI1_0 / NC*
SDI0_1 / NC* 12 46 SDI0_0 / NC*
AO_TRIG_OUT 13 47 EXTWFTRG
AI_TRIG_OUT 14 48 EXTDTRIG
GPTC1_SRC1549 DGND
GPTC0_SRC1650 DGND
GPTC0_GATE1751 GPTC1_GATE
GPTC0_OUT1852 GPTC1_OUT
GPTC0_UPDOWN 19 53 GPTC1_UPDOWN
EXTTIMEBASE 20 54 DGND
AFI1 21 55 AFI0
PB7 22 56 PB6
PB5 23 57 PB4
PB3 24 58 PB2
PB1 25 59 PB0
PC72660 PC6
PC52761 PC4
DGND 28 62 DGND
PC32963 PC2
PC13064 PC0
PA7 31 65 PA6
PA5 32 66 PA4
PA3 33 67 PA2
PA1 34 68 PA0
Table 3-1: VHDCI-type (68-pin) Connector Pin Assignment
- DAQ-/DAQe-/PXI 1
- 2016/2010/2006/2005 1
- Getting service 3
- Using this manual 5
- 1.3 Conventions 6
- Table of Contents 7
- List of Tables 9
- List of Figures 10
- List of Figures v 11
- 1 Introduction 13
- 1.1 Features 14
- 1.2 Applications 15
- 1.3 Specifications 16
- System Noise: (Typical) 17
- Gain error: 20
- 2005/2006/2016 20
- Ω typical 21
- 10 Introduction 22
- Ω for DAQ-/DAQe-/PXI-2010 23
- °C to 55°C 24
- °C to 80°C 24
- 1.4 Software Support 25
- DAQ-LVIEW PnP: LabVIEW Driver 26
- D2K-OCX: ActiveX Controls 26
- 2 Installation 27
- 16 Installation 28
- 2.3 Card Layout 29
- DAQ-2016/2010/2006/2005 30
- PXI-2016/2010/2006/2005 30
- 2.4 PCI Configuration 31
- 20 Installation 32
- 3 Signal Connections 33
- VHDCI-type (68-pin) Connector 34
- *PIO means programmable I/O 36
- SSI Connector (J3) 37
- Types of signal sources 38
- Single-Ended Measurements 38
- Differential Measurements 39
- 28 Signal Connections 40
- 4 Operation Theory 41
- 34 Operation Theory 46
- Ch1 with unipolar ±10V 46
- Ch2 with bipolar ±2.5V 46
- Ch4 with bipolar ±1.25V 46
- 36 Operation Theory 48
- Figure 4-3: Scan Timing 48
- Trigger Modes 49
- PSC_counter = 0 50
- Operation Theory 39 51
- 40 Operation Theory 52
- Operation Theory 41 53
- Figure 4-9: Middle-Trigger 53
- 42 Operation Theory 54
- Figure 4-10: Post trigger 54
- Operation Theory 43 55
- Figure 4-11: Delay trigger 55
- 44 Operation Theory 56
- Operation Theory 45 57
- 46 Operation Theory 58
- 4.2 D/A Conversion 59
- Software Update 60
- Timed Waveform Generation 61
- 50 Operation Theory 62
- 52 Operation Theory 64
- Operation Theory 53 65
- DLY2_Counter = 0 65
- 54 Operation Theory 66
- Operation Theory 55 67
- Figure 4-20: Stop Mode I 67
- 56 Operation Theory 68
- Figure 4-21: Stop Mode II 68
- Figure 4-22: Stop Mode III 68
- 4.3 Digital I/O 69
- 58 Operation Theory 70
- Figure 4-23: Mode 1 Operation 70
- Operation Theory 59 71
- Figure 4-24: Mode 2 Operation 71
- 60 Operation Theory 72
- Figure 4-25: Mode 3 Operation 72
- Figure 4-26: Mode 4 Operation 72
- Operation Theory 61 73
- Figure 4-27: Mode 5 Operation 73
- Figure 4-28: Mode 6 Operation 73
- 62 Operation Theory 74
- Figure 4-29: Mode 7 Operation 74
- Figure 4-30: Mode 8 Operation 74
- 4.5 Trigger Sources 75
- Operation Theory 65 77
- 66 Operation Theory 78
- Operation Theory 67 79
- 68 Operation Theory 80
- DAQ timing signals 81
- 72 Operation Theory 84
- 74 Operation Theory 86
- AI_Trig_Out and AO_Trig_Out 87
- 76 Operation Theory 88
- 5 Calibration 89
- 5.2 Auto-calibration 90
- Warranty Policy 91
- 80 Warranty Policy 92
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