Adlink PCI-7300A Manual de usuario Pagina 31
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Valorado. / 5. Basado en revisión del cliente
Registers 19
Legend:
X DI_CSR: Digital input control & status register
X DO_SCR: Digital output control & status register
X AUX_DIO: Auxiliary digital I/O port
X INT_CSR: Interrupt control and status register
X DI_FIFO: DI FIFO direct access port
X DO_FIFO: DO FIFO direct access port
X FIFO_CR: FIFO almost empty/full programming register
X POL_CTRL: Polarity control register for the control signals
Caution:
X I/O port is 32-bit width
X 8-bit or 16-bit I/O access is not allowed.
- 80MB Ultra-High Speed 32-CH 1
- Digital I/O Boards 1
- User’s Manual 1
- Getting Service from ADLINK 3
- Table of Contents 5
- Table of Contents iii 7
- Table of Contents v 9
- List of Tables 11
- List of Figures 12
- 1 Introduction 13
- 1.1 Applications 14
- 1.2 Features 14
- 1.3 Specifications 15
- 4Introduction 16
- 1.4 Software Support 17
- PCIS-VEE: HP-VEE Driver 18
- DAQBench 18
- : ActiveX Controls 18
- 2 Installation 19
- 2.2 Unpacking 20
- 2.4 PCI-7300A's Layout 21
- 10 Installation 22
- Installation 11 23
- 2.6 Connector Pin Assignment 24
- 14 Installation 26
- 2.7 Wiring and Termination 27
- Connect with DIN-100S 28
- Connect with DIN-502S 28
- 3Registers 29
- 3.1 I/O Port Base Address 30
- Registers 19 31
- Registers 21 33
- Registers 23 35
- 24 Registers 36
- Bit # 31~8 Don’t Care 36
- Registers 25 37
- 26 Registers 38
- Bits 76543210 38
- Bit # 7~0 DI_FIFO_8 38
- Bit # 15~8 DI_FIFO_16 38
- Bit # 31_16 DI_FIFO_32 38
- Registers 27 39
- Bit # 7~0 DO_FIFO_8 39
- Bit # 15~8 DO_FIFO_16 39
- Bit # 31_16 DO_FIFO_32 39
- 28 Registers 40
- Bit 15~0 PB_PAE_PAF 40
- Bit 31_16 PA_PAE_PAF 40
- Register 41
- 30 Registers 42
- 4 Operation Theory 43
- 4.2 Block Diagram 44
- 4.3 Digital I/O Data Flow 45
- 34 Operation Theory 46
- 4.5 Bus-mastering DMA 47
- 36 Operation Theory 48
- 4.6 Scatter/gather DMA 49
- 4.7 Clocking Mode 50
- Operation Theory 39 51
- 4.8 Starting Mode 52
- 4.9 Active Terminator 52
- Operation Theory 41 53
- 42 Operation Theory 54
- Operation Theory 43 55
- 44 Operation Theory 56
- Operation Theory 45 57
- 46 Operation Theory 58
- Continuous Digital Input 59
- 48 Operation Theory 60
- Operation Theory 49 61
- 50 Operation Theory 62
- Operation Theory 51 63
- 52 Operation Theory 64
- Operation Theory 53 65
- 54 Operation Theory 66
- Pattern Generator 67
- 4.12 Auxiliary DIO 68
- 5 C/C++ Libraries 69
- 5.2 Programming Guide 70
- 5.3 _7300_Initial 71
- @ Return Code 72
- 5.4 _7300_Close 73
- 5.5 _7300_Configure 74
- 5.6 _7300_DI_Mode 76
- 5.7 _7300_DO_Mode 77
- 5.8 _7300_AUX_DI 79
- 5.9 _7300_AUX_DI_Channel 80
- 5.10 _7300_AUX_DO 81
- 5.11 _7300_AUX_DO_Channel 82
- 5.12 _7300_Alloc_DMA_Mem 83
- 5.13 _7300_Free_DMA_Mem 84
- 5.14 _7300_DI_DMA_Start 85
- @ Syntax 86
- @ Argument 87
- 5.15 _7300_DI_DMA_Status 89
- 5.16 _7300_DI_DMA_Abort 90
- 5.17 _7300_GetOverrunStatus 91
- 5.18 _7300_DO_DMA_Start 92
- 5.19 _7300_DO_DMA_Status 94
- 5.20 _7300_DO_DMA_Abort 95
- 5.21 _7300_DO_PG_Start 96
- C/C++ Libraries 85 97
- DMADscrBadAlign 97
- 5.22 _7300_DO_PG_Stop 98
- 5.23 _7300_DI_Timer 99
- 5.24 _7300_DO_Timer 100
- 5.25 _7300_Int_Timer 101
- 5.26 _7300_Get_Sample 102
- 5.27 _7300_Set_Sample 103
- 5.28 _7300_GetUnderrunStatus 104
- Appendix 105
- Mode Definition 107
- 96 Appendix 108
- Appendix 97 109
- 98 Appendix 110
- Warranty Policy 111
- 100 Warranty Policy 112
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