Adlink PCIe-7360 Manual de usuario

Advance Technologies; Automate the World.Manual Rev.: 2.00Revision Date: Aug. 2, 2013Part No: 50-11042-1000PCIe-7360100 MHz 32-CH High-Speed Digita

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Introduction 1PCIe-73601 IntroductionADLINK’s PCIe-7360 is a high-speed digital I/O board with32-channel bi-directional parallel I/O lines. Data rate

2 Introduction1.3 Specifications1.3.1 General1.3.2 Digital I/OInterface x4 PCI Express interfaceConnectorsSMB Jack Connector x2 (CLK IN & OUT)68-

Introduction 3PCIe-7360Buffer sizeDigital input: 8k samplesDigital output: 20k samplesData transferSoftware pollingBus-mastering DMA with scatter-g

4 Introduction1.3.3 Application Function I/O (AFI)1.3.4 Timing SpecificationsChannels 8Direction (programmable)Input or output, per channel basisLogi

Introduction 5PCIe-7360Internal clock rate (programmable)1526 Hz – 100 MHz (100 MHz/ N; 1N65,535)Ext. frequency rangePhase shift disabled: 0-200 MH

6 Introduction1.3.5 Timing AccuracyAcquisition TimingChannel-to-Cannel skew ±1.08 nsSetup time to sampled clock (tSU) 2 nsHold time to sampled clock

Introduction 7PCIe-7360Figure 1-1: Acquisition Timing DiagramDI Sampled Clock (AFI7)tAF7D= Time delay of external sampled clock from A

8 IntroductionFigure 1-2: Generation Timing DiagramD0DO Sampled Clock (internal)DO DataWrite data to external devicetSC2AF6= Time delay from samp

Introduction 9PCIe-73601.3.6 External Clock I/O Specification1.3.7 I2C Master SpecificationCLK IN (SMB Jack Connector)Destination DI or DO sample clo

ii Revision HistoryRevision Release Date Description of Change(s)2.00 Aug. 2, 2013 Initial release

10 Introduction1.3.8 SPI Master SpecificationTransfer size of Data 0 - 4 BytesTransfer size of Cmd/ Addr 0 - 4 BytesLogic families(programmable)1.8 V

Introduction 11PCIe-73601.4 Software SupportADLINK provides versatile software drivers and packages forusers’ different approach to building up a

12 Introduction1.5 Schematics, I/O and Indicators.Figure 1-3: PCIe-7360 Schematic Diagram1.6 ConnectorsThe PCIe-7360 card is equipped with one 68-pin

Introduction 13PCIe-7360I/O, and two SMB connectors for sample clock input and output,as labeled on the faceplate.Figure 1-4: PCIe-7360 Connectors

14 Introduction ID Pin Pin IDGND 68 34 GND(DI CLK) AFI7 67 33 AFI6 (DO CLK)GND 66 32 GNDD0 65 31 D1AFI5 64 30 AFI4D2 63 29 D3GND 62 28 GNDD4 61 27 D5

Introduction 15PCIe-7360Table 1-1: PCIe-7360 SCSI-VHDCI 68-pin AssignmentD28 37 3 D29GND 36 2 GNDD30 35 1 D31Pin SignalSignal TypeDirection Descript

16 IntroductionTable 1-2: Signal Descriptions for SCSI-VHDCI and SMB Connectors33 AFI6Control/DataI/OApplication Function I/O, can be configured as:

Introduction 17PCIe-7360Table 1-3: SMB Jack Connector Signal Description1.7 LED indicatorThe LED on the faceplate indicates I2C & SPI communicat

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Getting Started 19PCIe-73602 Getting Started2.1 Unpacking ChecklistBefore unpacking, check the shipping carton for any damage. Ifthe shipping carton

Preface iiiPCIe-7360PrefaceCopyright ©2013 ADLINK Technology, Inc.This document contains proprietary information protected by copy-right. All rights

20 Getting Started5. Secure the card to the chassis with a screw.6. Replace the system/chassis cover.7. Connect the power plug to a power source, the

Operations 21PCIe-73603 OperationsThe PCIe-7360 provides functions including high-speed digitalpattern acquisition, digital pattern generation, appli

22 Operations.Figure 3-1: PCIe-7360 Block Diagram3.2 Programmable Logic LevelTo interface different logic level applications, the PCIe-7360 sup-ports

Operations 23PCIe-7360level. When connecting PCIe-7360 to a device under test (DUT),interface voltage levels must be compatible, as follows.X VIH: Th

24 OperationsDI Raw Data MappingFor digital pattern acquisition, the data width can be configured to8-bit, 16-bit, 24-bit, or 32-bit and the data tra

Operations 25PCIe-7360Figure 3-2: DI Raw Data Mapping for 8-Bit Data Width

26 OperationsFigure 3-3: DI raw data Mapping for 16-Bit Data Width

Operations 27PCIe-7360Figure 3-4: DI raw data Mapping for 24-Bit Data WidthFigure 3-5: DI raw data Mapping for 32-Bit Data Width3.4 Sample Clock Phas

28 Operationsother words, the phase shift of sample clock is 4.5° x N, where N isany integer from 1 to 80. Furthermore, in phase shifting mode, thesu

Operations 29PCIe-73603.5 Bus-mastering DMA Data TransferDigital I/O data transfer between PCIe-7360 and PC’s systemmemory is through bus mastering D

iv PrefaceConventionsTake note of the following conventions used throughout thismanual to make sure that users perform certain tasks andinstructions

30 Operationsdue to the complexity of programming DMA transfer mode, It isrecommended that a high-level program library provided by ourdriver be used

Operations 31PCIe-7360Figure 3-8: Scatter-Gather DMA for Data TransferChoose Finite or Continuous OperationData can be transferred continuously to or

32 Operationsclock). DI sample clock can be selected as the following two clocksources:X Internal DI sample clock – the PCIe-7360 can internally gene

Operations 33PCIe-7360Digital Output (DO) Sample ClockFor the operation of digital pattern generation in continuous modeor burst handshake mode, PCIe

34 OperationsFigure 3-9: DI/DO Sample Clock Architecture80-stepphase shiftIAFI71/NDI CLKMuxInt. DI sampled clk80-stepphase shiftDI Sampled CLKAcquisi

Operations 35PCIe-7360Table 3-2: DI/DO Sample Clock Configuration3.7 Operating ModesThe PCIe-7360 supports four different modes for acquisition andg

36 Operationscan be selected from internal or external clock source. The opera-tion sequences are listed as follows:Steps:X Define DI port configurat

Operations 37PCIe-7360Operating architecture of DI DMA in continuous mode is asshown.Figure 3-10: DI Continuous Mode ArchitectureTiming of DI DMA in

38 OperationsFigure 3-11: DI Timing DiagramDO DMA in Continuous ModeFor the DO pattern generation operation in continuous mode,PCIe-7360 card can gen

Operations 39PCIe-7360Z PCIe-7360 can also export DO sample clock to external devices. The destination of DO sample clock exporting can be AFI6 or SM

Table of Contents vPCIe-7360Table of ContentsRevision History... iiPreface ...

40 OperationsFigure 3-12: DO Continuous Mode ArchitectureTiming of DO DMA in continuous mode is as shown.1/NDO CLKMuxInt. DO sampled clk80-stepphase

Operations 41PCIe-7360Figure 3-13: DO Timing DiagramDI DMA in Handshake ModeFor the DI pattern acquisition operation in handshake mode,PCIe-7360 card

42 Operationsnal (DI-REQ and DI-ACK) of external device to the AFI3 and AFI4.X Define DI starting mode configuration (NoWait or WaitTRIG)Z If choose

Operations 43PCIe-7360Figure 3-14: DI Handshake Mode ArchitectureTiming of DI DMA in handshake mode is as shown.Bus Master DMA8kS FIFO Flip FlopD[31:

44 OperationsFigure 3-15: DI Handshake Timing DiagramDO DMA in Handshake ModeFor the DO pattern generation operation in handshake mode,PCIe-7360 card

Operations 45PCIe-7360nal (DO-REQ and DO-ACK) of external device to the AFI3 and AFI4.X Define DO starting mode configuration (NoWait or Wait-TRIG)Z

46 OperationsThe operating architecture of DO DMA in handshake mode is asshown.Figure 3-16: DO Handshake Mode Architecture80-stepphase shiftExt. DI s

Operations 47PCIe-7360Timing of DO DMA in handshake mode is as shown.Figure 3-17: DO Handshake Timing DiagramDI DMA in Burst Handshake ModeThe burst

48 OperationsStep1: ConfigurationX Define DI port configuration (32/24/16/8-bits data width)X Define DI logic level configuration (3.3/2.5/1.8 V)X De

Operations 49PCIe-7360Step2: Execute DI DMA Read Command (burst handshake mode)X PCIe-7360 will generate DI-ACK signal when it is ready to receive DI

vi Table of Contents3.6 Sample Clock... 31Digital Input (DI) Sample Clock ...

50 OperationsTiming of DI DMA in burst handshake mode is as shown.Figure 3-19: DI Burst Handshake Timing DiagramDO DMA in Burst Handshake ModeIn DO b

Operations 51PCIe-7360Z The PCIe-7360 can also export DO sampled clock to external devices. The destination of the exported DO sampled clock can be A

52 OperationsFigure 3-20: DO Burst Handshake Mode Architecture1/NDO CLKMuxInt. DO sampled clk80-stepphase shiftExt. DO sampled clkExt. DO CLK MuxBus

Operations 53PCIe-7360Timing of DO DMA in burst handshake mode is as shown.Figure 3-21: DO Burst Handshake Timing DiagramDO DMA in Burst Handshake Mo

54 Operations3.8 Trigger Source and Trigger ModeThe PCIe-7360 supports 2 trigger sources, software commandtrigger and external digital trigger, to st

Operations 55PCIe-7360[Example 2] External digital trigger with post trigger DO data Count: 8 samplesTrigger Event: DO-Start (rising edge)Re-Trigger

56 Operations[Example 4] External digital trigger with post trigger and re-trig-gerDO data Count: 4 samples per triggerTrigger Event: DO-Start (risin

Operations 57PCIe-7360[Example 6] External digital trigger with gated triggerDO data Count: 12 samplesTrigger Event: DO-Pause (logic high)Figure 3-28

58 OperationsTrigger outDI_SW O DO_SW O EventPM O COS O HandshakeDI-REQ I DI-ACK O DI-TRIG I 

Operations 59PCIe-7360ExternalTrigger inDI-Start IDI Start Trigger in– External digital trigger signal to begin an acquisition operation.DO-Start IDO

List of Figures viiPCIe-7360List of FiguresFigure 1-1: Acquisition Timing Diagram ... 7Figure 1-2: Generat

60 OperationsHandshakeDI-REQ IDigital Input Reques– In handshake mode for DI pattern acquisition, DI-REQ carries handshake control information from D

Operations 61PCIe-7360ClockDI-SCLK I/OExternal DI Sampled Clock in– In free-running mode or burst handshake mode, PCIe-7360 can receive external samp

62 OperationsI2C MasterPCIe-7360’s application function I/O (AFI) can be configured asI2C node for communicating with peripheral devices throughPCIe-

Operations 63PCIe-7360Address or Data). Figure 3-29 shows the data transfer on the I2Cbus.Figure 3-30: Data Transfer on the I2C BusI2C master of PCIe

64 OperationsI2C Cmd/Addr Count is less than 4 byte:I2C Data Count is less than 4 byte:Figure 3-31: I2C Data FormatSPI MasterPCIe-7360’s application

Operations 65PCIe-7360Figure 3-32: SPI Master of PCIe-7360SPI MasterAFI0AFI1PCIe-7360 CardSlave 0AFI2AFI3SCKSCKSD0SISDIS0CS#0 CS0

66 OperationsSPI master of PCIe-7360 provide at most 64 bits -- 32 bitsaddress/ command and 32 bits data. SPI master of PCIe-7360supports only one sl

Operations 67PCIe-7360External Digital TriggerPCIe-7360 supports external digital trigger mode to start or pausean acquisition or generation operatio

68 OperationsTrigger OutPCIe-7360’s Application Function I/O (AFI) can be configured astrigger output when receiving a software start command of digi

Operations 69PCIe-7360Event OutPCIe-7360’s Application Function I/O (AFI) can be configured asevent output of pattern match or COS (Change of State).

viii List of FiguresFigure 3-35: External Digital Trigger Input Configuration... 67Figure 3-36: Configured AFI as Internal Software

70 OperationsHandshakePCIe-7360’s Application Function I/O (AFI) can be configured ashandshake mode (DI-REQ/DI-ACK/DI-TRIG/DO-REQ/DO-ACK/DO-TRIG) to

Operations 71PCIe-7360Sample Clock In/OutThe AFI of PCIe-7360 can be configured to sample clock in/outpin. For more details, please see Section 3.6 S

72 OperationsFigure 3-40: Configured AFI6 as DO Sampled Clock In/Out3.10 Pattern MatchPCIe-7360 supports pattern match function to monitor the datain

Operations 73PCIe-7360An example of 9 channel (CH0 – CH8) pattern match operation isshown. All of the enabled DI channel’s signal logic states is com

74 OperationsFigure 3-41: Example of Pattern Matching3.11 COS (Change of State) EventPCIe-7360 supports COS (Change of State) Event to monitor ifther

Operations 75PCIe-7360In COS mode, the DI data are sampled by 125 MHz clock rate.Therefore, the pulse width of the DI data should be longer than8ns.

76 Operationsby the DUT is almost the same as the output voltage of thePCIe-7360.The input impedance of the PCIe-7360 is 10 k, which is a highimpeda

ADLINK DIN-68H 77PCIe-7360Appendix A ADLINK DIN-68HThe DIN-68H is a terminal board designed for PCIe-7360 to pro-vide the easier wiring for test ci

78 ADLINK DIN-68HAll jumpers on DIN-68H are used for the setting of pull-up or pull-down resistor termination. The proper termination setting canredu

ADLINK DIN-68H 79PCIe-7360The DIN-68H also provides the option of user define pull-up resis-tor termination. Please note that the pad position of th

List of Tables ixPCIe-7360List of TablesTable 1-1: PCIe-7360 SCSI-VHDCI 68-pin Assignment ... 15Table 1-2: Signal Descriptions for S

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Important Safety Instructions 81PCIe-2602Important Safety InstructionsFor user safety, please read and follow all instructions,WARNINGS, CAUTIONS,

82 Important Safety InstructionsX Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.A Lithium-type batter

Getting Service 83PCIe-7360Getting ServiceContact us should you require any service or assistance. ADLINK Technology, Inc. Address: 9F, No.166 Ji

84 Getting ServiceADLINK Technology, Inc. (French Liaison Office) Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France Tel: +33 (0) 1 60 12